1. Field of the Invention
The present invention relates to a silicon-on-insulator (SOI) and more particularly to a SOI substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to remove a floating body effect without a separate layout space.
2. Description of Related Art
In general, a wide isolation region is required in the process for fabricating complementary metal oxide semiconductor (CMOS) transistors to prevent latch-up of the CMOS transistors and to isolate the transistors. However, the wide isolation region results in larger size and low integration of a semiconductor device. In order to solve the aforementioned problem, a SOI technique has been disclosed to fabricate a SOI transistor, which has proved to be superior to a bulk silicon transistor by providing a lower power consumption rate and in an application to a performance VLSI.
FIG. 1 is a schematic cross-sectional view of a conventional SOI CMOS transistor. As shown in FIG. 1, the conventional SOI CMOS transistor includes a buried oxide layer 12 on a mono-silicon substrate 10; a N-type mono-silicon layer 14 for a P type transistor, a P-type mono-silicon layer 16 for a N type transistor and an isolation layer 18 for separating those layers on the buried oxide layer. A gate oxide layer is inserted to a predetermined part of the thin layer 14 to form a gate electrode 20. A lightly doped drain (LDD) structure of source/drain regions is formed at both sides of the gate electrode 20 in the thin layer 14. Also, a gate oxide layer is inserted at a predetermined part of the thin layer 16 to form a gate electrode 22. An LDD structure of source/drain regions is formed at both sides of the gate electrode 22 in the thin layer 16.
In the conventional SOI CMOS transistor thus constructed, there is a reduction in the junction areas between the source/drain region of the P type transistor and the body region 15 and between the source/drain region of the N type transistor and the body region 17 to reduce junction capacitance in these source/drain regions. In addition, the P and N type transistors are isolated by the isolation layers 18, so that there is no problem like latch-up. Accordingly, the SOI CMOS transistor can be superior to the bulk silicon CMOS transistor in rapid and stable operations of a circuit. Also, the body regions 15, 17 of the thin layers 14, 16 are not electrically connected, but floated to eliminate the reverse body effect, which increase the operational speed of the circuit.
However, the floating body regions 15, 17 may cause fluctuations in voltage, which leads to many problems such as a kink effect, low breakdown voltage of a drain due to a parasitic horizontal bi-polar transistor, dynamic leakage of current and an output characteristic of history dependence and instability in the SOI CMOS transistor.
In order to solve the aforementioned problems, there have been disclosed many methods, one of which is a body contact to fix the unstably operating body regions at a specific level of voltage. An effective body contact should result in a low resistance. Unfortunately, it is quite difficult to make an effective body contact in the SOI CMOS transistor, and a H type body contact is the most frequently used one at present. However, if the width of channels increases in the H type body contact, the resistance of the body contact also increases. Thus, it is difficult to effectively set the unstable body region at a specific level of voltage. Because the resistance of the body contact varies along with changes in the width of channels, great efforts should be made in designing and verifying the circuit. Since a modification and insertion of an additional separate space are required for designing the H type body contact on the conventional bulk silicon substrate, it will not be easy to make a migration from the CMOS transistor applied to the bulk silicon substrate to the SOI CMOS transistor in the designing step. Even if various types of body contacts have been suggested in addition to the H type body contact in recent years, the newly suggested body contacts have exhibited operational failures or many other problems in the fabricating processes, similar to or worse than the H type body contact.
Therefore, it is an object of the invention to provide a SOI substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to migrate the design applied to a conventional bulk silicon substrate to the SOI design and to eliminate a floating body effect.
According to one aspect of the invention, there is provided a SOI substrate which includes a mono-silicon substrate and a buried oxide layer formed over the entire surface of the mono-silicon substrate. A thin mono-silicon layer is formed over the entire surface of the buried oxide layer, and conductive layers are formed at through holes of the buried oxide layer positioned between the predetermined regions of the thin layer and the substrate for body contacts.
Preferably, the conductive layers can be made of heavily doped mono-silicon or polysilicon or metal. For instance, the conductive layers can be made of tungsten.
In another aspect of the invention, there is provided a method for fabricating a SOI substrate. First and second mono-silicon substrates are provided, and a buried oxide layer is formed over the entire surface of the second substrate. An ion implantation layer is formed to be positioned at a predetermined distance internally apart from the surface of the second substrate to restrict a mono-silicon thin layer between the buried oxide layer and the ion implantation layer. Through holes are formed at the buried oxide layer at respective predetermined areas of the thin layer. Conductive layers are formed at the through holes for body contacts of the thin layer. The first and second substrates at both sides of the buried oxide layer are combined, and the first substrate is detached from the thin layer using the ion implantation layer.
The step of forming the conductive layers may further include forming conductive layers on the buried oxide layer to fill up the through holes and levelling off the conductive layers of the through holes with the buried oxide layer.
The conductive layer can be made of heavily doped mono-silicon, poly-silicon or metal. Specifically, the conductive layer can be made of tungsten. The conductive layer can also be made into a mono-silicon layer formed by an epitaxial growth.
In accordance with another aspect of the present invention, there is provided a SOI MOSFET. The MOSFET includes a first conductivity mono-silicon substrate having a second conductivity well region and a second conductivity remaining region of a first conductive layer. A buried oxide layer is formed over the entire surface of the substrate. A first conductivity thin mono-silicon layer is formed on the buried oxide layer positioned at a predetermined part of the remaining substrate. A second conductivity thin mono-silicon layer is formed on the buried oxide layer positioned at a predetermined part of the well region of the substrate. An isolation layer is formed on the buried oxide layer between the first and second thin layers for separation. A first conductive layer is formed at the through hole of the buried oxide layer under a part of the first thin layer for the body contact of the first thin layer. A second conductive layer is formed at the through hole of the buried oxide layer under a part of the second thin layer for the body contact of the first thin layer. A first transistor is formed on the first thin layer, and a second transistor is formed on the second thin layer.
In one embodiment, the SOI MOSFET includes first voltage supply means formed at the through hole of the isolation layer and the buried oxide layer positioned at a predetermined part of the remaining area of the substrate. Second voltage supply means is formed at the through hole of the isolation layer and the buried oxide layer positioned at a predetermined part of a well region.
The first voltage supply means can be constructed with a third conductive layer in the through hole of the buried oxide layer and a fifth conductive layer in the through hole of the isolation layer. Also, the second voltage supply means can be constructed with a fourth conductive layer in the through hole of the buried oxide layer and a sixth conductive layer in the through hole of the isolation layer. The first voltage supply means can have a seventh conductive layer in the through hole of the buried oxide layer and the isolation layer, and the second voltage supply means can have an eighth conductive layer in the through hole of the buried oxide layer and the isolation layer. A first conductive plug is formed to reduce resistance at the remaining area under the first conductive layer and the first voltage supply means, and a second conductive plug is formed to reduce resistance at the well region under the second conductive layer and the second voltage supply means. In one embodiment, the first voltage supply means is for voltage Vss, and the second voltage supply means is for voltage VDD.
In one embodiment, the first, second, third and fourth conductive layers are made of an identical material. The material can be heavily doped mono-silicon, poly-silicon or metal. The first and third conductive layers can be made of the first conductivity type of mono-silicon or poly-silicon layer, and the second and fourth conductive layers can be made of the second conductivity type of mono-silicon or poly-silicon layer. The metal layer can be made of tungsten. The fifth and sixth conductive layers can be made of the same material, but different from the first, second, third and fourth conductive layers. The seventh and eighth conductive layers can be made of the same material, but different from the first and second conductive layers. The fifth, sixth, seventh and eighth conductive layers can be made of metal layers of aluminum or copper.
In accordance with the invention, conductive layers are formed on the buried oxide layer between the active regions of thin layers and the substrate to eliminate the floating body effect without a separate layout space. In addition, since there is a constant body contact resistance regardless of changes in the length and width of channels in the SOI MOSFET, no great effort is required to design and verify the SOI circuit. That is, it is easier to make a migration from the bulk silicon substrate to the SOI substrate without any specific modification in design.